Sequence Detector - abab_baba (Structural Modelling)

D-Flipflop

Behavioural Description

library ieee;
use ieee.std_logic_1164.all;

package D_FF is
    component dFlipFlop is
        port(reset, inp, clock : in std_logic;
            y : out std_logic);
    end component;
end package D_FF;


-----------------------------D Flip Flop-------------------------

library ieee;
use ieee.std_logic_1164.all;

entity dFlipFlop is
port(reset, inp, clock : in std_logic;
        y : out std_logic);
end entity dFlipFlop;

architecture struct of dFlipFlop is
begin

    process(clock)
    begin
        if (clock = '1' and clock' event) 
        then
            if reset = '1' 
            then
                y <= '0';
            else
                y <= inp;
            end if;
        end if;
    end process;

end struct;

Sequence Detector - abab_baba

Structural Modelling

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.D_FF.all;

entity seqDetector is
port(reset, inp, clock : in std_logic; --inp=0 => a inp1=1 => b
        y : out std_logic);
end entity seqDetector;

architecture struct of seqDetector is

    signal d0, d1, d2, q0, q1, q2, q0_bar, q1_bar, q2_bar, inp_bar : std_logic;
begin
    q0_bar <= not q0;
    q1_bar <= not q1;
    q2_bar <= not q2;
    inp_bar <= not inp;
    
    
    ------------------Here we are defining the combinational block L1 whoich is the input to the FF0----------------
    d0 <= (not reset) and ((inp_bar and q1_bar) or (q2_bar and q1_bar and q0) 
    or (q2_bar and q0 and inp_bar) or (q2 and q0_bar and inp_bar));
    

    ------------------D Flip Flop 0--------------------------------
    dFlipFlop_0 : dFlipFlop port map(reset, d0, clock, q0);
    
    
    
    ------------------Here we are defining the combinational block L2 whoich is the input to the FF1----------------
    d1 <= (not reset) and ((q2_bar and inp) or (q1_bar and inp));
    
    ------------------D Flip Flop 1--------------------------------
    dFlipFlop_1 : dFlipFlop port map(reset, d1, clock, q1);
    
    
    
    ------------------Here we are defining the combinational block L3 whoich is the input to the FF2----------------
    d2 <= (not reset) and ((q2_bar and inp_bar and q1) or (q0_bar and inp_bar and q1) or (q2 and q1_bar and inp));
    
    ------------------D Flip Flop 2--------------------------------
    dFlipFlop_2 : dFlipFlop port map(reset, d2, clock, q2);


    ------------------Here goes the output------------------------------
    y<= q2 and ((q1_bar and q0 and inp) or (q1 and q0_bar and inp_bar));

end struct;

DUT

-- A DUT entity is used to wrap your design.
--  This example shows how you can do this for the
--  Full-adder.

library ieee;
use ieee.std_logic_1164.all;
entity DUT is
   port(input_vector: in std_logic_vector(2 downto 0);
        output_vector: out std_logic_vector(0 downto 0));
end entity;

architecture DutWrap of DUT is
   component seqDetector is
    port(reset, inp, clock : in std_logic;
        y : out std_logic);
    end component;
begin

   -- input/output vector element ordering is critical,
   -- and must match the ordering in the trace file!
   seq_instance: seqDetector 
            port map (
                    -- order of inputs Cin B A
                    reset => input_vector(2),
                    inp   => input_vector(1),
                    clock   => input_vector(0),
                                        
                    
                    y => output_vector(0));

end DutWrap;

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TRACEFILE

TRACEFILE