4-bit Adder-Subtractor

(i) - VHDL Description

You have been given a full adder description in the reference design. Using this full adder as a component, describe a 4-bit ripple carry adder-subtractor in VHDL.

info

It is a simple binary adder-subtractor that can be implemented by cascading four 1-bit full adders such that the the carry generated by the addition of lower significant bits forms the incoming carry for addition of the next significant bits.

If M = 0, output will be A + B
If M = 1, output will be A - B

(ii) Simulation

Simulate the adder using the generic testbench to confirm the correctness of your description. To do this, note that you need to use the given tracefile and modify the testbench given to you appropriately.

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Tracefile format
<a3 a2 a1 a0><b3 b2 b1 b0><M> <Cout><S> 11111
Tracefile 📃