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Mux

Part-A: 2x1 Mux​

(i) VHDL description​

Write the VHDL description of a 2-1 multiplexer as shown in figure below.

(ii) SImulation​

Simulate the 2x1 multiplexer using the generic testbench to confirm the correctness of your description. To do this, use the tracefile given below and modify the testbench given to you appropriately.

Tracefile format
<In1><In2><S> <Y> 1 (Updated)
Tracefile 📃

Part-B: 4x1 Mux​

(i) VHDL description​

Write the VHDL description of a 4x1 multiplexer using above described 2x1 Mux.

(ii) SImulation​

Simulate the 4x1 multiplexer using the generic testbench to confirm the correctness of your description. To do this, use the tracefile given below and modify the testbench given to you appropriately.

Tracefile format
<In4><In3><In2><In1><S2><S1> <Y> 1
Tracefile 📃

Part-C: 4-bit 4x1 Mux​

(i) VHDL description​

Write the VHDL description of a 4-bit 4x1 multiplexer using above described 4x1 Mux.

(ii) SImulation​

Simulate the 4-bit 4x1 multiplexer using the generic testbench to confirm the correctness of your description. To do this, use the tracefile given below and modify the testbench given to you appropriately.

Tracefile format
<d3d2d1d0><c3c2c1c0><b3b2b1b0><a3a2a1a0><sel1sel0> <Y3Y2Y1Y0> 1111
Tracefile 📃