Decoder

2 to 4 decoder

VHDL description

Describe a 2 to 4 decoder with enable input in VHDL as shown in figure below. (Assume enable high input)

Simulation

Simulate the decoder using the generic testbench to confirm the correctness of your description. To do this, note that you need to write the tracefile and modify the testbench given to you appropriately.

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Tracefile format
<A1 A0><E> <Y3 Y2 Y1 Y0> 1111
Tracefile 📃